Hardware

CLP Security Modules

CLP-36: IPsec/SRTP Offload Engine

The CLP-36 core is a cost reduced IPsec/SRTP offload engine aimed at mobile handsets, PDAs and gateways which now routinely support IPsec at bit rates in the 10-30 Mbps range. Based on the silicon proven CLP-25, the core combines hash and cryptographic engines, a special purpose DMA engine, and ESP/AH packet processing logic to offload most of the IPsec protocol from the host processor. The SDMA block reduces bandwidth on the system bus through dual targeting of the hash and encryption cores. An extended crypto offload capability has been added to the engine to support both AES-XCBC and AES-f8 algorithms required for SRTP processing in VoIP.

Key Features:

• AH & ESP mode processing for IPsec
• AES-CBC mode cipher supporting 128, 192 and 256-bit key sizes
• DES-CBC mode cipher supporting 56 and 168-bit (3DES) key sizes
• HMAC-MD5 and HMAC-SHA-1 mode hash
• Transport mode and tunnel mode processing
• Extended Sequence Numbers
• Crypto offload - allows access to the ciphers and hash cores in the engine
• AES-CTR, AES-XCBC, AES-f8, SHA-1/MD5, and DES/3DES
• Scatter-gather DMA based packet memory architecture
• 23% overall area reduction when compared to the CLP-25
• Gate count of 164K ASIC gates
• Memory requirement reduced by two thirds

Applications:

• IPsec and SRTP (VoIP)
• Mobile Handsets
• Personal Digital Assistants
• Wireless access points and gateways

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