Hardware

CLP Security Modules

CLP-35: High Throughput XTS-AES Cipher Core

The IEEE is developing two new security standards for 'data at rest' in disk and tape storage applications. As a replacement for the AES-LRW algorithm, the IEEE 1619 committee is now set to standardize on a new tweakable narrow-block cipher designated as XTS-AES. XTS is defined by the IEEE as the XEX-based Tweaked CodeBook mode (TCB) with CipherText Stealing algorithm.

Key Features:

• Throughput up to 10 Gbps for SAS-G1 through G3 and Fibre Channel applications
• Scalable throughput up to 30 Gbps also available
• Implements XTS-AES (also referred to as AES-XTS) as specified in draft IEEE standard P1619-D17
• Fully compliant with P1619D17, with optional support for ciphertext stealing (CTS) mode
• Support for 2 key sizes for the AES core - 128 and 256 bits (as per P1619D17)
• Gate count of 132K ASIC gates
• Test bench and sample synthesis scripts provided

Applications:

• Disk/storage and RAID encryption
• Serial Attached SCSI (G1 through G3)
• Fibre Channel (all currently defined traffic rates)

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