Hardware
CLP Security Modules
CLP-35: High Throughput XTS-AES Cipher Core
The IEEE has developed two new security standards for 'data at rest' in disk and tape storage applications. As a replacement for the AES-LRW algorithm, the IEEE Std 1619-2007 committee has designated a new tweakable narrow-block cipher known as XTS-AES. XTS is defined by the IEEE as the XEX-based Tweaked Code Book mode (TCB) with CipherText Stealing algorithm.
Key Features:
- Throughput up to 10 Gbps for SAS-G1 through G3 and Fibre Channel applications
- Scalable throughput up to 30 Gbps also available
- Implements XTS-AES (also referred to as AES-XTS) as specified in IEEE Std 1619-2007
- Fully compliant with IEEE Std 1619-2007, with optional support for ciphertext stealing (CTS) mode
- Support for 2 key sizes for the AES core - 128 and 256 bits
- Gate count of 132K ASIC gates
- Test bench and sample synthesis scripts provided
Applications:
- Disk/storage and RAID encryption
- SATA drives - disk and solid state
- Serial Attached SCSI (G1 through G3)
- Fibre Channel (all currently defined traffic rates)

