Hardware
CLP Security Modules
CLP-31: Suite B Elliptic Curve Accelerator
Suite B is a collection of algorithms defined by the U.S. National Security Agency which are mandated to fully protect national security information. The NSA complemented the Advanced Encryption Standard (AES) with algorithms for hashing, digital signatures and key exchange with the goal of normalizing the security level of each algorithm and encouraging interoperability both domestically and internationally. Elliptic has optimized an FPGA configuration of its silicon proven CLP-23 public key accelerator to address the offload requirement for Elliptic Curve Digital Signature Algorithm (ECDSA) and Elliptic Curve key exchange algorithms (ECDH and ECMQV).
Key Features:
- Offloads the computationally intensive parts of public key cryptography
- Adaptable to multiple FPGA families including Xilinx, Lattic and Altera
- Can be integrated alongside Elliptic hashing and encryption cores required for Suite B
- Dual clock domains for interface circuitry and ALU maximizes integration flexibility
- Core acts as a processor peripheral
- Library support for ECDSA and ECDH
- Optional support for RSA 4096 and 8192 operations
Applications:
- Military communication systems
- Government communication systems
- VPN Appliances
- Link security
The resources required to implement the CLP-31 in various Xilinx FPGAs is shown in the table below:
| Spartan 3 S3-1500-4 |
Virtex 4 V4LX160-10 |
Virtex 2 V2-4000-4 |
Virtex 2 V2-6000-6 |
|
|---|---|---|---|---|
| Max core clk (MHz) | 56 | 74 | 67 | 90 |
| BRAM | 8 | 8 | 8 | 8 |
| Registers | 3293 | 3025 | 2734 | 3206 |
| Multipliers1 | 4 | 4 | 4 | 4 |
| LUTs | 3300 | 3300 | 3300 | 3300 |
Note: 1. Throughput stated for 128 bit keys.
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