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Hardware
CLP Security Modules
CLP-47: Configurable XTS-AES Cipher Core
The IEEE has ratified two new security standards for 'data at rest' in disk and tape storage applications. For rotating and solid state disks, the standard is known as IEEE Std 1619-2007. It specifies a new tweakable narrow-block cipher designated as XTS-AES. XTS is defined as the XEX-based Tweaked CodeBook mode (TCB) with CipherText Stealing algorithm.
Key Features:
- Implements XTS-AES (also referred to as AES-XTS) compliant to IEEE Std 1619-2007
- Configurable flow-through solution with core build options to optimize performance versus gate count:
- Build options for 2, 5, 7, 10 or 14 XTS-AES cores - see product brief for more details
- Selectable between 2 key sizes for the AES core - 128- and 256-bits
- Optional ciphertext stealing (CTS) mode if required
- Gate count ranges from 70k to 410k ASIC gates
- Performance up to 2 Gbytes/s (16 Gb/s)
- Targeted solution for SATA 3.0Gb/s (SATA II) rates
Applications:
- Flash or solid state disk drives
- Disk/storage and RAID encryption
- Serial Attached SCSI (G1 through G3)
- Fibre Channel (all currently defined traffic rates)
